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TSMC and ASML push High NA EUV toward 12-inch photomasks, with a pilot line by 2031

TSMC also said it intends to start using ASML's High NA machines in high-volume manufacturing in 2030, as the companies seek support from mask makers and chipmakers.

By · Editor

· Archive story, added · 3 min read · ✓ Fact-checked

The 60-second brief

  • 1On September 8, 2026, TSMC and ASML announced an industry initiative to shift High NA EUV lithography to 12-inch photomasks.
  • 2The plan targets a 12-inch mask pilot line by 2031 and system readiness for advanced-node production by 2033.
  • 3TSMC said it intends to use ASML's High NA technology in high-volume manufacturing starting in 2030.

The news

On September 8, 2026, Taiwan Semiconductor Manufacturing Co. (TSMC; TSM) and ASML Holding (ASML) announced an industry initiative to move High NA EUV chipmaking from current 6-inch masks to 12-inch photomasks, targeting a pilot line by 2031 to raise productivity and cut costs.

EUV (extreme ultraviolet) lithography machines print chip patterns onto silicon wafers, and High NA (high numerical aperture) is ASML's newest, finer-resolution generation. A photomask is the master template holding each layer's pattern. The companies said they formed the initiative on September 7, ahead of the SPIE BACUS photomask conference in Monterey, California.

According to the joint announcement, the initiative aims to establish a 12-inch mask pilot line by 2031, supporting full lithography system readiness for advanced-node production by 2033. The companies said High NA EUV adopters and other major suppliers had expressed interest in joining. They said larger masks are expected to raise fab productivity, lower chipmaking costs and remove stitching constraints, but gave no figures.

Stitching is the workaround the larger mask is meant to end. The Register reported that ASML designed High NA optics to stay compatible with 6-inch masks, which halves the exposure field compared with earlier EUV machines, so large chips must be printed as two separately exposed patterns joined together.

TSMC also set a date for its own adoption. It said it intends to use ASML's High NA technology in high-volume manufacturing for advanced nodes starting in 2030, and expects more chip layers to need High NA as nodes advance, mainly because AI chips require more complex transistor structures. ASML Chief Executive Christophe Fouquet said 12-inch masks "enable greater scanner productivity."

The numbers

Current photomask size
6-inch
Proposed photomask size
12-inch
TSMC High NA high-volume manufacturing start
2030
12-inch mask pilot line target
2031
Lithography system readiness for advanced-node production
2033
Possible system productivity gain (ASML CTO estimate, per TechNode)
About 40%

Why CEOs should care

For companies designing custom AI chips, this is a roadmap issue for the 2030s, not a near-term procurement issue. Large accelerator dies are the ones most exposed to High NA's half-size exposure field. Engineering and sourcing leads should ask their foundry how die size limits, stitching and mask costs will work on High NA nodes between 2030 and 2033, before any 12-inch masks exist, and build that into long-range chip plans.

For CFOs and boards at photomask, mask blank, inspection and lithography suppliers, a format change of this size resets product roadmaps and capital plans. The initiative sets milestones, but neither company disclosed funding, cost savings or which suppliers had committed. TechNode reported that ASML Chief Technology Officer Marco Pieters estimated system productivity could rise by about 40% if the transition succeeds, a forward-looking estimate rather than a measured result.

For boards and investors tracking AI hardware costs, the signal is that TSMC and ASML see lithography productivity, not just more machines, as a lever on chip prices after 2030. Treat the dates as targets; industry-wide format changes depend on many suppliers moving together.

The bigger picture

TSMC had held back on High NA. The Register reported that TSMC had not adopted it even for its 2-nanometer process, while Intel Foundry already uses it; TrendForce, citing ASML, reported that Intel has processed more than one million wafers with High NA EUV. TechNode reported that Samsung Electronics confirmed it would take part in the larger-mask effort and plans High NA for high-volume DRAM production from 2028, and that SK hynix was evaluating participation.

The logic is that High NA's half-size exposure field hurts most on the large processors behind AI demand, the chips most likely to need stitching. A larger mask is meant to remove that constraint while keeping High NA's finer resolution. Whether suppliers of mask blanks, mask-writing and inspection tools, and pellicles (protective films that cover masks) can move to a new format on the same schedule will decide whether the 2033 date holds.

What happened next

As of September 29, 2026, TSMC's newsroom had posted no further update on the initiative. What to watch: which mask makers and equipment suppliers formally join, and any standards work on the new format; TSMC's third-quarter earnings conference on October 15, 2026, for detail on its 2030 High NA plans; and progress toward the 2031 pilot line.

Written by

Editor · Technology & Business Writer

Hussein is a writer and business technology enthusiast focused on the intersection of technology, entrepreneurship, finance, artificial intelligence, and digital innovation.

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How this story was made. Researched from primary sources such as company announcements and filings, with the help of technology tools, fact-checked twice, and approved for publication by Hussein Mukhtar.

Published by Tech CEO Daily, an independent publication. Masthead · Editorial standards · Report an error

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